The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2024

Filed:

Oct. 19, 2020
Applicants:

Stmicroelectronics (Research & Development) Limited, Marlow, GB;

Stmicroelectronics (Grenoble 2) Sas, Grenoble, FR;

Inventors:

Ivelina Hristova, Edinburgh, GB;

Pascal Mellot, Lans en Vercors, FR;

Neale Dutton, Edinburgh, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 7/50 (2017.01); G06F 1/10 (2006.01); G06T 15/08 (2011.01); G06T 15/00 (2011.01); G01S 7/4865 (2020.01); G01S 17/894 (2020.01); G01S 7/4863 (2020.01);
U.S. Cl.
CPC ...
G01S 7/4865 (2013.01); G01S 7/4863 (2013.01); G01S 17/894 (2020.01); G06F 1/10 (2013.01); G06T 7/50 (2017.01); G06T 15/005 (2013.01); G06T 15/08 (2013.01); G06T 2207/10108 (2013.01);
Abstract

A depth map sensor includes a first array of first pixels, each first pixel having a first photodetector associated with a pixel circuit that comprises a plurality of first bins for accumulating events. A clock source is configured to generate a plurality of phase-shifted clock signals. A first circuit has a plurality of first output lines coupled to the first array of first pixels. The first circuit is configured to receive the plurality of phase-shifted clock signals. The first circuit includes a first block and a second block. The first block is configured to propagate the plurality of phase-shifted clock signals to the second block during a first period determined by a first enable signal and the second block configured to select to which of the plurality of first output lines each of the plurality of phase-shifted clock signals is applied.


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