The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2024

Filed:

Aug. 29, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Takuya Kusaka, Yokohama Kanagawa, JP;

Hirosuke Narai, Tokyo, JP;

Kazunori Masuda, Yokohama Kanagawa, JP;

Makoto Iwai, Chigasaki Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2896 (2013.01); G01R 31/2853 (2013.01); G01R 31/2884 (2013.01); H01L 23/5386 (2013.01); H01L 24/48 (2013.01); H01L 25/0657 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 2224/48147 (2013.01); H01L 2224/48149 (2013.01); H01L 2224/48229 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1438 (2013.01);
Abstract

A semiconductor device includes first and second chips in a package. A first pad is on the first chip and electrically connected to a node between a power supply pad and a ground pad on the first chip. Second and third pads are on the second chip. An internal wiring connects the first pad to the second pad within the package. A power circuit on the semiconductor chip configured to supply a current to the second pad. A switch is on the second chip between the second pad and the power supply circuit to connect or disconnect the second pad from the power circuit. A control circuit is on the second chip and configured to output a first signal for the switch in response to a test signal supplied to the third pad and a second signal to the power circuit to cause the power circuit to output current.


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