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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11889721 B1

PDFFull Text
Date of Patent:
Jan. 30, 2024

Filed:

Jul. 16, 2019

Display substrate, manufacturing method thereof and display device

Applicants:

Ordos Yuansheng Optoelectronics Co., Ltd., Inner Mongolia, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Feng Li, Beijing, CN;

Yezhou Fang, Beijing, CN;

Assignees:

ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., Inner Mongolia, CN;

BOE TECHNOLOGY GROUP CO., LTD., Beijing, CN;

Attorney:

Lippes Mathias LLP

Primary Examiner:

Victoria K Hall

Int. Cl.
CPC ...
H01L 27/32 (2006.01); H01L 51/00 (2006.01); H01L 51/56 (2006.01); H10K 59/123 (2023.01); G02F 1/1362 (2006.01); H10K 59/124 (2023.01); H10K 71/00 (2023.01); H10K 71/20 (2023.01); H01L 27/12 (2006.01); G02F 1/163 (2006.01); H10K 59/12 (2023.01); G02F 1/1333 (2006.01);
U.S. Cl.
CPC ...
H10K 59/123 (2023.02); G02F 1/136227 (2013.01); H01L 27/1259 (2013.01); H01L 27/1288 (2013.01); H10K 59/124 (2023.02); H10K 71/00 (2023.02); H10K 71/231 (2023.02); G02F 1/133357 (2021.01); G02F 2001/1635 (2013.01); G02F 2201/123 (2013.01); H10K 59/1201 (2023.02); H10K 71/233 (2023.02);
Abstract

A method of manufacturing a display substrate includes: forming a switch unit on a base substrate; forming a planarization layer on one side of the switch unit away from the base substrate, wherein a region, corresponding to an output electrode, of the planarization layer is provided with a planarization layer via hole, and an orthographic projection of the planarization layer via hole onto the base substrate is located within an orthographic projection region of the output electrode onto the base substrate; etching a surface of a region, corresponding to the planarization layer via hole, of the output electrode; and forming a pixel electrode on one side of the planarization layer away from the switch unit, wherein the pixel electrode is in contact with the output electrode through the planarization layer via hole.

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