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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11889218 B1

PDFFull Text
Date of Patent:
Jan. 30, 2024

Filed:

Sep. 10, 2021

Stacked substrate solid state image sensor

Applicant:

Sony Group Corporation, Tokyo, JP;

Inventors:

Shunichi Sukegawa, Ibaraki, JP;

Shunji Maeda, Tokyo, JP;

Junichi Ishibashi, Saitama, JP;

Motoshige Okada, Kanagawa, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:

Wolf, Greenfield & Sacks, P.C.

Primary Examiner:

Twyler L Haskins

Assistant Examiner:

Akshay Trehan

Int. Cl.
CPC ...
H04N 25/772 (2023.01); H01L 27/146 (2006.01); H01L 27/14 (2006.01); H04N 23/65 (2023.01); H04N 25/70 (2023.01); H04N 25/75 (2023.01); H04N 25/76 (2023.01); H04N 25/79 (2023.01); H04N 25/71 (2023.01); H04N 25/709 (2023.01); G01S 17/10 (2020.01);
U.S. Cl.
CPC ...
H04N 25/772 (2023.01); H01L 27/14 (2013.01); H01L 27/146 (2013.01); H01L 27/14603 (2013.01); H01L 27/14609 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 27/14643 (2013.01); H01L 27/14645 (2013.01); H04N 23/65 (2023.01); H04N 25/70 (2023.01); H04N 25/745 (2023.01); H04N 25/75 (2023.01); H04N 25/76 (2023.01); H04N 25/79 (2023.01); G01S 17/10 (2013.01); H01L 27/1464 (2013.01); H01L 27/14621 (2013.01); H01L 27/14627 (2013.01); H04N 25/709 (2023.01);
Abstract

A solid state image sensor of the present disclosure includes: a first semiconductor substrate provided with at least a pixel array unit in which pixels that perform photoelectric conversion are arranged in a matrix form; and a second semiconductor substrate provided with at least a control circuit unit that drives the pixels. The first semiconductor substrate and the second semiconductor substrate are stacked, with first surfaces on which wiring layers are formed facing each other, the pixel array unit is composed of a plurality of divided array units, the control circuit unit is provided corresponding to each of the plurality of divided array units, and electrical connection is established in each of the divided array units, through an electrode located on each of the first surfaces of the first semiconductor substrate and the second semiconductor substrate, between the pixel array unit and the control circuit unit.

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