The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2024

Filed:

Feb. 14, 2022
Applicant:

Dv2js Innovation Llp., New Delhi, IN;

Inventors:

Mukul Sarkar, New Delhi, IN;

Neha Priyadarshini, New Delhi, IN;

Assignee:

DV2JS Innovation, LLP, New Delhi, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 25/75 (2023.01); H01L 27/146 (2006.01); H04N 25/59 (2023.01); H04N 25/778 (2023.01);
U.S. Cl.
CPC ...
H04N 25/75 (2023.01); H01L 27/14612 (2013.01); H01L 27/14643 (2013.01); H04N 25/59 (2023.01); H04N 25/778 (2023.01);
Abstract

A method and a system are disclosed for pixel-embedded signal amplification of a CMOS image sensor using multi-step voltage-gain enhancement. It involves activating a row of the CMOS image sensor by resetting switches SRST, SH1and SH2to charge nodes PD1, PD2, SD1, and SD2 to a pre-set voltage potential and VRST. The CMOS sensor switches OFF SRST, SH1and SH2for integration of the charges at PD1 for producing a corresponding photo-generated signal. This signal is sampled by transferring to a gate of source follower SF1, to produce an amplified signal. It further involves double-sampling the amplified signal for removing any pixel-offset variation to produce a resultant signal. The said method is repeated for second row of CMOS image sensor for implementing additional gain on the resultant voltage signal, and the same is finally converted to digital bits to obtain an output signal of with enhanced gain.


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