The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2024

Filed:

Dec. 01, 2021
Applicant:

Dual Helios Semiconductor Equipment Company, Inc., Jiaxing, CN;

Inventor:

Lawrence Chung-Lai Lei, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/18 (2006.01); H01L 31/048 (2014.01); H01L 31/075 (2012.01);
U.S. Cl.
CPC ...
H01L 31/18 (2013.01); H01L 31/0488 (2013.01); H01L 31/075 (2013.01);
Abstract

A system for wafer processing, includes: a frame comprising a frame opening; and a membrane configured to couple to the frame and to cover at least a part of the frame opening, the membrane comprising a membrane opening, wherein the membrane opening has a membrane opening area that is equal to or less than a frame opening area of the frame opening; wherein the membrane is configured for coupling with the wafer, wherein when the wafer is coupled with the membrane, the wafer covers the membrane opening, and wherein the membrane is configured to maintain the wafer at a certain position with respect to the frame; and wherein the membrane opening area is less than a total area of the wafer.


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