The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2024

Filed:

Jan. 12, 2018
Applicant:

Zedel Sàrl, Saint-Aubin-Sauges, CH;

Inventor:

Claude Meylan, Saint-Aubin-Sauges, CH;

Assignee:

ZEDEL SÀRL, Saint-Aubin-Sauges, CH;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 31/0312 (2006.01); H01L 31/107 (2006.01); H01L 27/146 (2006.01); H01L 31/18 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14649 (2013.01); H01L 27/14689 (2013.01); H01L 27/14698 (2013.01); H01L 31/0312 (2013.01); H01L 31/107 (2013.01); H01L 31/1812 (2013.01); H01L 31/1864 (2013.01); H01L 31/1892 (2013.01);
Abstract

Disclosed is a low temperature method of fabrication of short-wave infrared (SWIR) detector arrays (FPA) including a readout wafer and absorption layer connected for improved performances. The absorber layer includes a SWIR conversion layer with a GeSn or SiGeSn alloy. A first series of process steps realizes a CMOS processed readout wafer. A buffer layer is transferred on the readout wafer and annealed at temperatures compatible with the CMOS substrate, achieving a high quality crystalline buffer layer. The method assures a temperature profile between the light entrance surface of the buffer layer, and the readout electronics so the annealing temperature remains compatible with the CMOS. The buffer layer is used for further growth of a GeSn or SiGeSn structure to create the conversion layer and achieve the final structure of the SWIR FPA. Also disclosed is a SWIR FPA detector as realized by such method, and SWIR FPA applications.


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