The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2024

Filed:

Jun. 27, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Wonyoung Kim, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3185 (2013.01); H01L 21/561 (2013.01); H01L 23/49822 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 24/97 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02377 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/14134 (2013.01); H01L 2224/16225 (2013.01);
Abstract

A semiconductor package includes a semiconductor chip having chip pads on a first surface and having first and second side surfaces opposite to each other and third and fourth side surfaces opposite to each other, a molding member covering the third and fourth side surfaces and exposing the first and second side surfaces of the semiconductor chip, a redistribution wiring layer on a lower surface of the molding member to cover the first surface of the semiconductor chip and including a plurality of redistribution wirings electrically connected to the chip pads, and outer connection members arranged in a connection region defined on an outer surface of the redistribution wiring layer and electrically connected to the redistribution wirings.


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