The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2024

Filed:

Apr. 19, 2022
Applicant:

AU Optronics Corporation, Hsinchu, TW;

Inventors:

Ya-Jung Wang, Hsinchu, TW;

Jing-Wun Jhang, Hsinchu, TW;

Rong-Fu Lin, Hsinchu, TW;

Nien-Chen Li, Hsinchu, TW;

Hsien-Chun Wang, Hsinchu, TW;

Che-Chia Chang, Hsinchu, TW;

June Woo Lee, Hsinchu, TW;

Hsin-Ying Lin, Hsinchu, TW;

Chia-Ting Hsieh, Hsinchu, TW;

Chien-Fu Huang, Hsinchu, TW;

Sung-Yu Su, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/32 (2016.01);
U.S. Cl.
CPC ...
G09G 3/32 (2013.01); G09G 2330/021 (2013.01);
Abstract

A pixel array is provided. The pixel array includes a plurality of pixels, wherein each of the pixels includes a light emitting diode, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to the first transistor and an anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to the second transistor. The fourth transistor is coupled to an anode of a light emitting diode of an adjacent pixel, a control terminal of the third transistor, and a cathode of the light emitting diode. The fifth transistor is coupled to the cathode of the light emitting diode, and receives a second control signal and a system low voltage.


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