The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2024

Filed:

Sep. 01, 2022
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Ki Min Son, Paju-si, KR;

Seok Noh, Paju-si, KR;

Ki Bok Park, Paju-si, KR;

Ye Won Hong, Paju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01); H10K 59/131 (2023.01); G09G 3/3266 (2016.01); G11C 19/28 (2006.01); H10K 59/124 (2023.01);
U.S. Cl.
CPC ...
H10K 59/1315 (2023.02); G09G 3/2096 (2013.01); G09G 3/3266 (2013.01); G11C 19/28 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0291 (2013.01); G09G 2330/021 (2013.01); H10K 59/124 (2023.02);
Abstract

A display panel and an electronic device including the same are disclosed. A circuit layer of the display panel includes at least a first transistor and a second transistor. The first transistor includes a first oxide semiconductor pattern, a gate electrode, a first electrode in contact with one side of the first oxide semiconductor pattern, a second electrode in contact with the other side of the first oxide semiconductor pattern, and a first-first metal pattern disposed on the substrate to overlap the first oxide semiconductor pattern. The second transistor includes a second oxide semiconductor pattern, a gate electrode, a first electrode in contact with one side of the second oxide semiconductor pattern, a second electrode in contact with the other side of the second oxide semiconductor pattern, a first-second metal pattern disposed on the substrate to overlap the second oxide semiconductor pattern, and a second metal pattern disposed between the second oxide semiconductor pattern and the first-second metal pattern.


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