The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2024

Filed:

Aug. 16, 2021
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Sung Soo Kim, Gyeonggi-do, KR;

Woon Seob Lee, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H01L 23/48 (2006.01); H01L 23/535 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H10B 12/50 (2023.02); H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/535 (2013.01); H01L 23/53228 (2013.01); H01L 23/53257 (2013.01); H10B 12/09 (2023.02); H10B 12/315 (2023.02); H10B 12/34 (2023.02);
Abstract

A semiconductor device includes: an inter-layer dielectric layer over a substrate including a cell region, a first peripheral region, and a second peripheral region; a capping layer over the inter-layer dielectric layer; a capacitor capped by the inter-layer dielectric layer in the cell region; a contact plug penetrating the inter-layer dielectric layer in the first peripheral region; a metal interconnection formed over the contact plug through the capping layer; and a through electrode penetrating the capping layer and the inter-layer dielectric layer and extending into the substrate in the second peripheral region.


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