The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2024

Filed:

May. 20, 2022
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Abhishek Gupta, Bengalaru, IN;

Sayantan Gupta, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); H03K 3/3565 (2006.01); H03K 3/2893 (2006.01);
U.S. Cl.
CPC ...
H03K 3/3565 (2013.01); H03K 3/2893 (2013.01);
Abstract

A circuit includes an inverter coupled between an input and an output. The inverter includes first and second pull-down transistors having control terminals coupled to the input, a pull-up resistor, and a pull-up transistor having a control terminal coupled to the input. The first and second pull-down transistors are coupled in series along a pull-down path extending between a first voltage supply terminal and the output. The pull-up resistor and pull-up transistor are coupled in series along a pull-up path extending between a second voltage supply terminal and the output. A hysteresis transistor has a control terminal coupled to the output. The hysteresis transistor is coupled to the inverter along a hysteresis path extending between the first voltage supply terminal and the pull-up path. A clamp circuit is coupled to the inverter along a clamp path extending between the first voltage supply terminal and the pull-down path.


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