The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2024

Filed:

Oct. 27, 2021
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventor:

Eung San Cho, Torrance, CA (US);

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/07 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 23/3135 (2013.01); H01L 23/3121 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/24 (2013.01); H01L 25/072 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/2101 (2013.01); H01L 2224/221 (2013.01); H01L 2224/24137 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13064 (2013.01); H01L 2924/13091 (2013.01);
Abstract

A semiconductor package includes a package substrate that includes an interior laminate layer, a first metallization layer disposed below the interior laminate layer, and a second metallization layer disposed above the interior laminate layer, a first semiconductor die that includes a first load terminal disposed on a first surface of the first semiconductor die and a second load terminal disposed on a second surface of the first semiconductor die that is opposite from the first surface of the first semiconductor die, and a liner of dielectric material on the first semiconductor die, wherein the first semiconductor die is embedded within the interior laminate layer such that the first surface of the first semiconductor die faces the second metallization layer, and wherein the liner of dielectric material is disposed on a corner of the first semiconductor die that is between the first and second load terminals of the first semiconductor die.


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