The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2024

Filed:

Nov. 11, 2021
Applicant:

Socionext Inc., Kanagawa, JP;

Inventors:

Yasumitsu Sakai, Kanagawa, JP;

Shinichi Moriwaki, Kanagawa, JP;

Assignee:

SOCIONEXT INC., Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 17/12 (2006.01); G11C 5/06 (2006.01); G11C 11/4074 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01);
U.S. Cl.
CPC ...
G11C 17/12 (2013.01); G11C 5/063 (2013.01); G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01);
Abstract

A layout structure of a ROM cell using a complementary FET (CFET) is provided. The ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the first transistor and a ground power supply line, and second data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the second transistor and a ground power supply line.


Find Patent Forward Citations

Loading…