The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2024

Filed:

Nov. 11, 2021
Applicants:

SK Hynix Inc., Icheon, KR;

Korea Advanced Institute of Science and Technology, Daejeon, KR;

Inventors:

Kyunghyun Kim, Daejeon, KR;

Jino Seo, Uiwang, KR;

Hyukjin Lee, Suwon, KR;

SeongHwan Cho, Daejeon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G06F 7/544 (2006.01); H03M 1/74 (2006.01); G06F 7/50 (2006.01); G06F 7/523 (2006.01);
U.S. Cl.
CPC ...
G11C 11/40 (2013.01); G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06F 7/5443 (2013.01); H03M 1/74 (2013.01);
Abstract

A semiconductor device includes a memory cell array including a plurality of memory cells coupled between a multiplicity of word lines and one or more bit lines; and an operation circuit configured to perform a multiplication and accumulation (MAC) operation with one or more first multi-bit data provided from the one or more bit lines and one or more second multi-bit data, wherein a plurality of memory cells coupled to a bit line store a plurality of bits included in a corresponding one of the one or more first multi-bit data, and wherein the memory cell array sequentially provides the plurality of bits included in the corresponding first multi-bit data to the operation circuit.


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