The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2024

Filed:

Jun. 23, 2021
Applicant:

Vmware, Inc., Palo Alto, CA (US);

Inventors:

Nishchay Dua, Pleasanton, CA (US);

Andreas Nowatzyk, San Jose, CA (US);

Isam Wadih Akkawi, Santa Clara, CA (US);

Pratap Subrahmanyam, Saratoga, CA (US);

Venkata Subhash Reddy Peddamallu, Sunnyvale, CA (US);

Adarsh Seethanadi Nayak, San Jose, CA (US);

Assignee:

VMware, Inc., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0897 (2016.01); G06F 12/0831 (2016.01); G06F 12/0862 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0897 (2013.01); G06F 12/0833 (2013.01); G06F 12/0862 (2013.01); G06F 2212/152 (2013.01);
Abstract

The state of cache lines transferred into an out of caches of processing hardware is tracked by monitoring hardware. The method of tracking includes monitoring the processing hardware for cache coherence events on a coherence interconnect between the processing hardware and monitoring hardware, determining that the state of a cache line has changed, and updating a hierarchical data structure to indicate the change in the state of said cache line. The hierarchical data structure includes a first level data structure including first bits, and a second level data structure including second bits, each of the first bits associated with a group of second bits. The step of updating includes setting one of the first bits and one of the second bits in the group corresponding to the first bit that is being set, according to an address of said cache line.


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