The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2024

Filed:

Jun. 25, 2020
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Elliot H. Mednick, Boxborough, MA (US);

Edward McLellan, Boxborough, MA (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 1/324 (2019.01); G06F 12/0875 (2016.01); G06F 1/3293 (2019.01); G06F 1/3234 (2019.01); G06F 12/0811 (2016.01); G06F 11/16 (2006.01); G06F 1/3287 (2019.01); G06F 12/084 (2016.01); G06F 9/38 (2018.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 1/324 (2013.01); G06F 1/3243 (2013.01); G06F 1/3287 (2013.01); G06F 1/3293 (2013.01); G06F 3/065 (2013.01); G06F 3/068 (2013.01); G06F 3/0619 (2013.01); G06F 3/0625 (2013.01); G06F 11/1666 (2013.01); G06F 12/0811 (2013.01); G06F 12/0875 (2013.01); G06F 9/3009 (2013.01); G06F 9/3877 (2013.01); G06F 12/084 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/286 (2013.01); G06F 2212/452 (2013.01);
Abstract

A heterogeneous processor system includes a first processor implementing an instruction set architecture (ISA) including a set of ISA features and configured to support a first subset of the set of ISA features. The heterogeneous processor system also includes a second processor implementing the ISA including the set of ISA features and configured to support a second subset of the set of ISA features, wherein the first subset and the second subset of the set of ISA features are different from each other. When the first subset includes an entirety of the set of ISA features, the lower-feature second processor is configured to execute an instruction thread by consuming less power and with lower performance than the first processor.


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