The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2024

Filed:

Nov. 20, 2020
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Lan Yu, Albany, NY (US);

Benjamin D. Briggs, Clifton Park, NY (US);

Tyler Sherwood, Fonda, NY (US);

Raghav Sreenivasan, Fremont, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 5/08 (2006.01); H01L 33/46 (2010.01); H01L 23/48 (2006.01); H01L 33/10 (2010.01); G02F 1/1335 (2006.01); G02F 1/1362 (2006.01);
U.S. Cl.
CPC ...
G02B 5/0808 (2013.01); H01L 23/481 (2013.01); H01L 33/10 (2013.01); H01L 33/46 (2013.01); G02F 1/133553 (2013.01); G02F 1/136277 (2013.01);
Abstract

Processing methods may be performed to form a grounded mirror structure on a semiconductor substrate. The methods may include revealing a metal layer. The metal layer may underlie a spacer layer. The metal layer may be revealed by a dry etch process. The method may include forming a mirror layer overlying the spacer layer and the metal layer. The mirror layer may contact the metal layer. The method may also include forming an oxide inclusion overlying a portion of the mirror layer. The portion of the mirror layer may be external to the spacer layer.


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