The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2024

Filed:

Jun. 03, 2022
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Janet L Schneider, Bellevue, WA (US);

Paul Accisano, Seattle, WA (US);

Mark G. Kupferschmidt, Bothell, WA (US);

Kenneth Reneris, Kirkland, WA (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10N 60/12 (2023.01); G06F 30/394 (2020.01); G06N 10/20 (2022.01); H03K 3/38 (2006.01); H03K 19/195 (2006.01); H03K 19/20 (2006.01); H10N 60/80 (2023.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
H10N 60/12 (2023.02); G06F 30/394 (2020.01); G06N 10/20 (2022.01); H03K 3/38 (2013.01); H03K 19/195 (2013.01); H03K 19/20 (2013.01); H10N 60/805 (2023.02); G06F 2119/12 (2020.01);
Abstract

Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.


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