The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2024

Filed:

Sep. 01, 2021
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Rakesh Hariharan, Bangalore, IN;

Sumantha Manoor Madhyastha, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2020.01); G06F 1/08 (2006.01); H03K 21/08 (2006.01); G06F 115/02 (2020.01);
U.S. Cl.
CPC ...
H03K 19/177 (2013.01); G06F 1/08 (2013.01); H03K 21/08 (2013.01); G06F 2115/02 (2020.01);
Abstract

An system-on-a-chip ('SoC') is provided. In some examples, the SoC includes a processor and a plurality of timer circuit blocks including at least a first timer circuit block and a second timer circuit block. Each of the plurality of timer circuit blocks may be selectively coupled by at least one of a first programmable matrix and a second programmable matrix. In some examples, the first programmable matrix may be configured to couple a second trigger input of the first timer circuit block with a first trigger output of the second timer circuit block. In some examples, the second programmable matrix is configured to couple a second fault input of the first timer circuit block with a first fault output of the second timer circuit block.


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