The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2024

Filed:

Nov. 17, 2022
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

David Michael Rogers, Sunnyvale, CA (US);

Eric N. Mann, Sammamish, WA (US);

Eric Lee Swindlehurst, Marysville, WA (US);

Toru Miyamae, Nagoya, JP;

Timothy John Williams, Kirkland, WA (US);

Ryuta Nagai, Nagoya, JP;

Sungkwon Lee, Saratoga, CA (US);

Ravindra M. Kapre, San Jose, CA (US);

Mimi Xuefeng Zhao Qian, Campbell, CA (US);

Yan Yi, Mountain View, CA (US);

Dung Si Ho, Sunnyvale, CA (US);

Boo Chin-Hua, Penang, MY;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0285 (2013.01); H01L 27/0288 (2013.01);
Abstract

An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.


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