The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 2024
Filed:
Oct. 24, 2019
Applicant:
Soitec, Bernin, FR;
Inventor:
David Sotta, Grenoble, FR;
Assignee:
SOITEC, Bernin, FR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 23/00 (2006.01); H01L 33/00 (2010.01); H01L 21/20 (2006.01); H01L 25/065 (2023.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/94 (2013.01); H01L 21/02639 (2013.01); H01L 21/2007 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 33/0093 (2020.05); H01L 2224/94 (2013.01);
Abstract
A process for collectively fabricating a plurality of semiconductor structures comprises providing a substrate including a carrier having a main face, a dielectric layer on the main face of the carrier and a plurality of crystalline semiconductor growth islands on the dielectric layer. At least one crystalline semiconductor active layer is formed on the growth islands. After the step of forming the active layer, trenches are formed in the active layer and in the growth islands in order to define the plurality of semiconductor structures.