The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2024

Filed:

Mar. 29, 2021
Applicant:

GM Global Technology Operations Llc, Detroit, MI (US);

Inventors:

Muhammad H. Alvi, Troy, MI (US);

Ming Liu, Troy, MI (US);

Rashmi Prasad, Troy, MI (US);

Anthony M. Coppola, Rochester Hills, MI (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/473 (2006.01); H01L 25/065 (2023.01); H05K 7/20 (2006.01);
U.S. Cl.
CPC ...
H01L 23/473 (2013.01); H01L 25/0657 (2013.01); H05K 7/209 (2013.01); H05K 7/20936 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06589 (2013.01);
Abstract

A power module is provided and includes first stack, second stack, and third stacks of layers, a heat pipe, and at least one cold plate or heat sink. The third stack of layers is disposed between the first and second stacks of layers and includes a first semiconductor die, a second semiconductor die and a center spacer layer disposed between the first semiconductor die and the second semiconductor die. The heat pipe extends at least partially into the center spacer layer. The at least one cold plate or heat sink receives thermal energy from the first stack of layers and the second stack of layers. The first stack of layers, the second stack of layers, the third stack of layers, the heat pipe and the at least one cold plate or heat sink facilitate dual sided cooling of each of the first semiconductor die and the second semiconductor die.


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