The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2024

Filed:

Nov. 09, 2021
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Yu-Chung Lien, San Jose, CA (US);

Deepanshu Dutta, Fremont, CA (US);

Tai-Yuan Tseng, Milpitas, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); G11C 11/4096 (2006.01); G11C 11/408 (2006.01); G11C 11/4074 (2006.01); G11C 11/4076 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4096 (2013.01); G11C 11/4074 (2013.01); G11C 11/4076 (2013.01); G11C 11/4085 (2013.01); G11C 11/4087 (2013.01);
Abstract

A memory device with one or more planes having sub-blocks is disclosed. The memory device may further include a voltage switch transistor for each of sub-blocks. Additionally, the memory device may further include a row decoder for each of sub-blocks. As a result, an operation to two sub-blocks can be performed at different times. For example, using a row decoder and voltage switch transistor, a sub-block can be initially read, followed by a subsequent read of another sub-block using a separate row decoder and voltage switch transistor. By staggering the read operations through a time delay, the peak current Icc associated with the supply voltage can be reduced.


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