The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2024

Filed:

Nov. 16, 2021
Applicants:

SK Hynix Inc., Icheon, KR;

Seoul National University R&db Foundation, Seoul, KR;

Inventors:

Hae Rang Choi, Icheon, KR;

Sungjoo Yoo, Seoul, KR;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/54 (2006.01); G11C 11/4091 (2006.01); G06F 7/50 (2006.01); G11C 11/4096 (2006.01); G11C 11/4094 (2006.01); G11C 7/10 (2006.01); G11C 11/4063 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4091 (2013.01); G06F 7/50 (2013.01); G11C 7/1051 (2013.01); G11C 11/4063 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); G11C 11/54 (2013.01); G11C 7/1006 (2013.01);
Abstract

A semiconductor device includes a cell circuit including a plurality of memory arrays, and a control circuit configured to control the cell circuit. A memory array of the plurality of memory arrays has a plurality of sub-arrays including a first sub-array and a second sub array, and an array connecting circuit configured to connect bit lines of the first sub-array to respective corresponding bit lines of the second sub-array according to a copy signal. The semiconductor device may further include a partial sum circuit configured to perform charge sharing between a plurality of bit lines of the first sub-array.


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