The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2024

Filed:

Jun. 04, 2021
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Satish Sivaswamy, Fremont, CA (US);

Ashot Shakhkyan, Yerevan, AM;

Nitin Deshmukh, Monroe, WA (US);

Garik Mkrtchyan, Fremont, CA (US);

Guenter Stenz, Niwot, CO (US);

Bhasker Pinninti, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3947 (2020.01); G06F 9/355 (2018.01); G06F 9/50 (2006.01); G06F 30/347 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3947 (2020.01); G06F 9/3555 (2013.01); G06F 9/5061 (2013.01); G06F 30/347 (2020.01);
Abstract

Examples described herein provide a non-transitory computer-readable medium storing instructions, which when executed on one or more processors, cause the one or more processors to perform operations. The operations include generating a plurality of child processes according to a number of a plurality of partitions in an integrated circuit (IC) design for an IC die, each of the plurality of child processes corresponding to and assigned to a respective one of the plurality of partitions. The operations include transmitting each of the plurality of partitions to a respective one of the plurality of child processes for routing, each of the plurality of partitions comprising a placement of components for the IC design. The operations include receiving a plurality of routings from the plurality of child processes. The operations include merging the plurality of routings into a global routing for the IC design by assembling together to form a global routing.


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