The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2024

Filed:

Jan. 31, 2022
Applicant:

Analog Devices, Inc., Wilmington, MA (US);

Inventors:

Martin Kessler, Salem, MA (US);

Miguel A. Chavez, Cambridge, MA (US);

Lewis F. Lahr, Dover, MA (US);

William Hooper, Newton, MA (US);

Robert Adams, Acton, MA (US);

Peter Sealey, Cravens Arms, GB;

Assignee:

Analog Devices, Inc., Wilmington, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G05B 19/418 (2006.01); G06F 1/26 (2006.01); H04B 3/54 (2006.01); G05B 19/042 (2006.01); H04L 12/403 (2006.01); G06F 13/364 (2006.01); H04R 29/00 (2006.01);
U.S. Cl.
CPC ...
G06F 13/426 (2013.01); G05B 19/0421 (2013.01); G05B 19/0423 (2013.01); G05B 19/4185 (2013.01); G06F 1/26 (2013.01); G06F 1/266 (2013.01); G06F 13/364 (2013.01); G06F 13/4282 (2013.01); G06F 13/4291 (2013.01); G06F 13/4295 (2013.01); H04B 3/542 (2013.01); H04B 3/548 (2013.01); H04L 12/4035 (2013.01); H04B 2203/547 (2013.01); H04R 29/007 (2013.01); Y02D 10/00 (2018.01);
Abstract

Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.


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