The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2024

Filed:

Sep. 27, 2019
Applicant:

Inspur Suzhou Intelligent Technology Co., Ltd., Suzhou, CN;

Inventor:

Peng Wang, Suzhou, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G06F 30/30 (2020.01); G06F 11/27 (2006.01); G06F 30/33 (2020.01); G06F 11/273 (2006.01); G06F 11/25 (2006.01); G06F 11/08 (2006.01); G06F 9/445 (2018.01); G06F 30/333 (2020.01); G06F 9/48 (2006.01); G06F 11/00 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2855 (2013.01); G06F 30/30 (2020.01); G06F 9/445 (2013.01); G06F 9/48 (2013.01); G06F 11/008 (2013.01); G06F 11/25 (2013.01); G06F 11/27 (2013.01); G06F 11/273 (2013.01); G06F 11/2733 (2013.01); G06F 30/33 (2020.01); G06F 30/333 (2020.01);
Abstract

Disclosed is a JTAG-based burning device, including controllable switches arranged between a TDI terminal of a JTAG host and a first chip, and between two adjacent chips, and further including a master controllable switch module arranged between each chip and a TDO terminal of the JTAG host, wherein the JTAG host may, according to a received burning instruction, control corresponding input terminals of the controllable switches to be connected to corresponding output terminals and also control an output terminal of the master controllable switch module to be connected to the corresponding input terminal. Obviously, a JTAG chain can be automatically adjusted by controlling the connection relationship between input and output terminals of the corresponding switches by only building a circuit, so that firmware burning on different chips or chip combinations is realized without manual adjustment, thereby improving the test efficiency, and simplifying the circuit structure.


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