The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2024

Filed:

Feb. 16, 2022
Applicants:

Hongqisheng Precision Electronics (Qinhuangdao) Co., Ltd., Qinhuangdao, CN;

Avary Holding (Shenzhen) Co., Limited., Shenzhen, CN;

Inventor:

Jun Dai, Qinhuangdao, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H01L 23/06 (2006.01); H01F 27/22 (2006.01); H01F 27/29 (2006.01); H01F 27/32 (2006.01); H01F 27/255 (2006.01); H05K 3/46 (2006.01); H05K 1/03 (2006.01); H05K 3/00 (2006.01); H05K 3/18 (2006.01);
U.S. Cl.
CPC ...
H05K 3/467 (2013.01); H05K 1/0298 (2013.01); H05K 1/0313 (2013.01); H05K 3/0023 (2013.01); H05K 3/188 (2013.01); H05K 2203/06 (2013.01); H05K 2203/0723 (2013.01);
Abstract

A circuit board includes a substrate, a first circuit layer, a second circuit layer, and a third circuit layer. The substrate includes a base layer, a first metal layer formed on the base layer, and a seed layer formed on the first metal layer. The first circuit layer is located on the substrate and includes the first metal layer and a signal layer formed on a surface of the first metal layer. The second circuit layer is coupled to the first circuit layer and includes the first metal layer, the seed layer, and a connection pillar formed on a surface of the first metal layer and the seed layer. The third circuit layer is coupled to the second circuit layer and includes the seed layer and a coil formed on a surface of the seed layer.


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