The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 2024
Filed:
Apr. 29, 2022
Applicant:
Infineon Technologies Ag, Neubiberg, DE;
Inventors:
Assignee:
Infineon Technologies AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/207 (2006.01); H01L 29/32 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7786 (2013.01); H01L 21/0254 (2013.01); H01L 21/26546 (2013.01); H01L 29/04 (2013.01); H01L 29/0684 (2013.01); H01L 29/1029 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/207 (2013.01); H01L 29/32 (2013.01); H01L 29/66462 (2013.01);
Abstract
A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.