The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2024

Filed:

Jul. 26, 2021
Applicant:

Excellence Opto. Inc., Miaoli County, TW;

Inventors:

Fu-Bang Chen, Miaoli County, TW;

Chih-Chiang Chang, Miaoli County, TW;

Chang-Ching Huang, Miaoli County, TW;

Chun-Ming Lai, Miaoli County, TW;

Wen-Hsing Huang, Miaoli County, TW;

Tzeng-Guang Tsai, Miaoli County, TW;

Kuo-Hsin Huang, Miaoli County, TW;

Assignee:

EXCELLENCE OPTO. INC., Hsinchu Science Park, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 29/00 (2006.01); H01L 21/66 (2006.01); H01L 25/16 (2023.01); H01L 29/866 (2006.01); H01L 33/64 (2010.01); H01L 33/52 (2010.01); H01L 33/62 (2010.01); H01L 33/42 (2010.01);
U.S. Cl.
CPC ...
H01L 22/32 (2013.01); H01L 25/167 (2013.01); H01L 29/866 (2013.01); H01L 33/42 (2013.01); H01L 33/52 (2013.01); H01L 33/62 (2013.01); H01L 33/64 (2013.01);
Abstract

The invention comprises a light emitting diode chip and a package substrate. The light emitting diode chip is provided with a semiconductor epitaxial structure, a lateral extending interface structure, a chip conductive structure, an N-type electrode located above the semiconductor epitaxial structure and a P-type bypass detection electrode located on the lateral extending interface structure. The chip conductive structure is provided with a P-type main electrode located on a lower side. The package substrate comprises a plurality of electrode contacts through which the N-type electrode, the P-type bypass detection electrode and the P-type main electrode are connected, and a process quality of a alternative substrate adhesive layer in one of the semiconductor epitaxial structure and the chip conductive structure and a chip-substrate bonding adhesive layer between the P-type main electrode and the package substrate is evaluated by detecting electrical characteristics.


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