The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2024

Filed:

May. 12, 2020
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Yuto Yakubo, Atsugi, JP;

Seiya Saito, Atsugi, JP;

Tatsuya Onuki, Atsugi, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 7/12 (2006.01); H10B 12/00 (2023.01); G11C 11/401 (2006.01);
U.S. Cl.
CPC ...
G11C 7/12 (2013.01); H10B 12/20 (2023.02); H10B 12/312 (2023.02); G11C 11/401 (2013.01);
Abstract

A semiconductor device is provided which includes a first control circuit including a first transistor in a silicon substrate channel, a second control circuit provided over the first control circuit, a memory circuit provided over the second control circuit, and a global bit line and an inverted global bit line that have a function of transmitting a signal between the first control circuit and the second control circuit. The first control circuit includes a sense amplifier circuit including an input terminal and an inverted input terminal. In a first period for reading data from the memory circuit to the first control circuit, the second control circuit controls whether the global bit line and the inverted global bit line from which electric charge is discharged are charged or not in accordance with the data read from the memory circuit.


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