The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2024

Filed:

Feb. 18, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hojun Chang, Seoul, KR;

Hundae Choi, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4076 (2006.01); G11C 11/4093 (2006.01); H03K 3/017 (2006.01); H01L 25/18 (2023.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G11C 11/4093 (2013.01); H03K 3/017 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01);
Abstract

A semiconductor memory device includes a mode register set and a clock correction circuit. The mode register set stores a first control code set. During a duty training interval based on a duty training command, the clock correction circuit may divide the duty training interval into a first interval, a second interval and a third interval which are consecutive, may correct a phase skew of a first clock signal and a third clock signal during the first interval, may correct a phase skew of a second clock signal and a fourth clock signal during the second interval, and may correct a phase skew of the first clock signal and the fourth clock signal during the third interval. The semiconductor memory device may enhance signal integrity of clock signals by correcting duty errors and phase skews of the clock signals having multi-phases during the duty training interval.


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