Memory controller including first processor for generating commands and second processor for generating logging information and method of operating the memory controller

Abstract

A memory controller is configured with a plurality of processors to be operated in parallel so that overhead of firmware may be reduced. The memory controller includes a first processor and a second processor. The first processor is configured to generate a command corresponding to a request received from a host and to translate a logical address included in the request into a physical address of a memory device. The second processor is configured to operate on data to be output to the memory device or on data received from the memory device. If the request is received from the host when the second processor is in an idle state, the first processor may control the second processor to release the idle state of the second processor and to perform an operation of logging command information corresponding to the request.