The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2024

Filed:

Jun. 20, 2022
Applicant:

Seagate Technology Llc, Fremont, CA (US);

Inventors:

Jon D. Trantham, Chanhassen, MN (US);

Praveen Viraraghavan, Chicago, IL (US);

John W. Dykes, Eden Prairie, MN (US);

Ian J. Gilbert, Chanhassen, MN (US);

Sangita Shreedharan Kalarickal, Eden Prairie, MN (US);

Matthew J. Totin, Excelsior, MN (US);

Mohamad El-Batal, Superior, CO (US);

Darshana H. Mehta, Shakopee, MN (US);

Assignee:

SEAGATE TECHNOLOGY LLC, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 29/08 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0616 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01); G11C 29/08 (2013.01);
Abstract

A data storage system can employ a read destructive memory configured with multiple levels. A non-volatile memory unit can be programmed with a first logical state in response to a first write voltage of a first hysteresis loop by a write controller prior to being programmed to a second logical state in response to a second write voltage of the first hysteresis loop, as directed by the write controller. The first and second logical states may be present concurrently in the non-volatile memory unit and subsequently read concurrently as the first logical state and the second logical state.


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