The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2024

Filed:

Jul. 17, 2020
Applicant:

The Regents of the University of Michigan, Ann Arbor, MI (US);

Inventors:

Valeria Bertacco, Ann Arbor, MI (US);

Abraham Addisie, Ann Arbor, MI (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 13/40 (2006.01); G06F 16/955 (2019.01); G06F 16/901 (2019.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); G06F 3/0655 (2013.01); G06F 13/4027 (2013.01); G06F 13/4282 (2013.01); G06F 16/9024 (2019.01); G06F 16/9558 (2019.01);
Abstract

The increased use of graph algorithms in diverse fields has highlighted their inefficiencies in current chip-multiprocessor (CMP) architectures, primarily due to their seemingly random-access patterns to off-chip memory. Here, a novel computer memory architecture is proposed that processes operations on vertex data in on-chip memory and off-chip memory. The hybrid computer memory architecture utilizes a vertex's degree as a proxy to determine whether to process related operations in on-memory or off-chip memory. The proposed computer memory architecture manages to provide up to 4.0× improvement in performance and 3.8× in energy benefits, compared to a baseline CMP, and up to a 2.0× performance boost over state-of-the-art specialized solutions.


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