Time-to-digital converter circuitry

Abstract

A time-to-digital converter (TDC) circuitry is disclosed for converting a phase difference between an input reference signal () and an input clock signal () to a digitally represented output signal (). The TDC circuitry comprises a plurality of constituent TDC:s (), a reference signal provider (), and a digital signal combiner (). Each constituent TDC is configured to convert a phase difference between a constituent reference signal () and a constituent clock signal () to a digitally represented constituent output signal (). The reference signal provider () is configured to provide the respective constituent reference signals () to each of the constituent TDC:s (). In at least a parallel operation mode of the TDC circuitry, each respective constituent reference signal comprises a respectively delayed version of the input reference signal () with different respective delays for at least two of the respective constituent reference signals. The digital signal combiner () is configured to provide the digitally represented output signal () based on the digitally represented constituent output signals () of the constituent TDC:s. A corresponding method and devices comprising the TDC circuitry are also disclosed.