The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2024

Filed:

Oct. 05, 2021
Applicant:

SK Hynix Inc., Icheon, KR;

Inventors:

Beom Seok Lee, Icheon, KR;

Won Jun Lee, Icheon, KR;

Seok Man Hong, Icheon, KR;

Assignee:

SK hynix Inc., Icheon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); H10B 63/00 (2023.01); G11C 13/00 (2006.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H10B 63/84 (2023.02); G11C 13/004 (2013.01); G11C 13/0004 (2013.01); G11C 13/0069 (2013.01); H10N 70/231 (2023.02); G11C 2213/71 (2013.01);
Abstract

A semiconductor device may include first row lines each extending in a first direction, column lines each extending in a second direction crossing the first direction, second row lines each extending in the first direction, a plurality of first memory cells respectively coupled between the first row lines and the column lines, each of the plurality of first memory cells including a first variable resistance layer and a first dielectric layer positioned between the first variable resistance layer and a corresponding one of the first row lines, and a plurality of second memory cells respectively coupled between the second row lines and the column lines, each of the plurality of second memory cells including a second variable resistance layer and a second dielectric layer positioned between the second variable resistance layer and a corresponding one of the second row lines.


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