The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2024

Filed:

Jan. 20, 2022
Applicant:

Pensando Systems Inc., Milpitas, CA (US);

Inventors:

Michael Brian Galles, Los Altos, CA (US);

Vipin Jain, San Jose, CA (US);

Assignee:

PENSANDO SYSTEMS INC., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 49/00 (2022.01); H04L 69/22 (2022.01); H04L 47/32 (2022.01); H04L 41/5019 (2022.01); H04L 45/74 (2022.01); H04L 47/6295 (2022.01);
U.S. Cl.
CPC ...
H04L 49/3018 (2013.01); H04L 41/5019 (2013.01); H04L 47/32 (2013.01); H04L 69/22 (2013.01); H04L 45/74 (2013.01); H04L 47/6295 (2013.01);
Abstract

A network appliance can have an input port that can receive network packets at line rate, two or more ingress queues, a line rate classification circuit that can place the network packets on the ingress queues at the line rate, a packet buffer that can store the network packets, and a sub line rate packet processing circuit that can process the network packets that are stored in the packet buffer. The line rate classification circuit can place a network packet on one of the ingress queues based on the network packet's packet contents. A buffer scheduler can select network packets for processing by a sub line rate packet processing circuit based on the priority levels of the ingress queues.


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