Analog-to-digital converter device and method capable of adjusting bit conversion cycle of analog-to-digital conversion operation

Abstract

An ADC device includes a DAC circuit, a comparator circuit, a SAR decision circuit, an oscillator circuit having a delay unit, and a processing circuit. The oscillator circuit is used for generating the clock signal according to a reset signal and a delay of the delay unit. The processing circuit is used for sequentially generating multiple bit conversion signals associated with multiple different bits of the decision signal, for generating at least one guard signal which follows the multiple bit conversion signals, and then for comparing the at least one guard signal with the reset signal to adjust the delay generated by the delay unit of the oscillator circuit.