Method for detecting rationality of pg pin power-on time sequence, system and related components

Abstract

A method, system, and related component for detecting properness of a PG pin power-on timing sequence are provided. The method comprises: obtaining a pull-up level of a PG pin of a VR chip (S); determining a value of a pull-up resistor of the PG pin, as a first resistance, when a current injected into the VR chip by using the pull-up level is equal to a maximum withstand current of the VR chip (S); obtaining an equivalent resistance to ground when the PG pin is at a low level, and calculating, based on the equivalent resistance to ground, a value of the pull-up resistor of the PG pin, as a second resistance, when an output voltage of the PG pin is equal to a preset interference voltage limit value (S); and outputting first prompt information when it is determined that an actual resistance of the pull-up resistor is lower than the first resistance or the second resistance (S). The foregoing solution is applied, to determine whether a power-on timing sequence of PG pins in a VR chip is proper, thereby avoiding an incorrect action of a subsequent circuit.