The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2024

Filed:

Feb. 04, 2021
Applicant:

Murata Manufacturing Co., Ltd., Kyoto, JP;

Inventors:

Hideyuki Sato, Kyoto, JP;

Koshi Himeda, Kyoto, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/30 (2006.01); H03F 1/08 (2006.01); H03F 3/213 (2006.01); H01L 27/102 (2023.01); H01L 29/737 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H03F 1/08 (2013.01); H01L 24/13 (2013.01); H01L 27/1022 (2013.01); H01L 29/7371 (2013.01); H03F 3/213 (2013.01); H01L 2224/13025 (2013.01); H01L 2924/13051 (2013.01); H01L 2924/1421 (2013.01); H03F 2200/447 (2013.01); H03F 2200/451 (2013.01);
Abstract

A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor that supplies a bias current based on a first current which is a part of a control current to the first transistor; a current output element in which a current flowing therethrough increases in accordance with a rise in temperature; and a wiring portion including a plurality of metal layers that are electrically connected to an emitter of the first transistor and that are stacked one on top of another so as to oppose the semiconductor substrate. At least one metal layer among the plurality of metal layers extends so as to overlap an area extending from at least a part of a first disposition area in which the first transistor is disposed to a second disposition area in which the current output element is disposed in plan view of the semiconductor substrate.


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