The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2024

Filed:

Oct. 22, 2019
Applicant:

Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Guangdong, CN;

Inventors:

Ziran Li, Shenzhen, CN;

Qianyi Zhang, Shenzhen, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66742 (2013.01); H01L 21/31116 (2013.01); H01L 21/823418 (2013.01); H01L 29/7869 (2013.01); H01L 29/78633 (2013.01);
Abstract

The present disclosure provides a method for fabricating a thin film transistor substrate, which includes: sequentially depositing a light shielding layer pattern, a buffer layer, an active layer pattern, a gate insulating layer, and a gate layer; wet etching the gate layer to form a gate layer pattern with a photoresist; stripping off the photoresist; forming a protective layer covering the gate layer pattern; etching the gate insulating layer to form a gate insulating layer pattern; and metalizing a non-channel region of the active layer pattern. This method can ensure that an orthographic projection of the gate layer pattern on the substrate completely coincides with that of the gate insulating pattern. Therefore, the entire active layer pattern is regulated by the gate layer pattern, thereby improving a turn-on current of a thin film transistor.


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