The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2024

Filed:

Jan. 21, 2020
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Susumu Obata, Yokohama, JP;

Keiichiro Matsuo, Yokohama, JP;

Mitsuo Sano, Yokohama, JP;

Kazuhito Higuchi, Yokohama, JP;

Kazuo Shimokawa, Yokohama, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 49/02 (2006.01); H01L 29/94 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H01L 28/92 (2013.01); H01L 29/945 (2013.01); H10B 12/038 (2023.02); H10B 12/373 (2023.02);
Abstract

According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, and a dielectric layer. The conductive substrate has a first main surface and a second main surface and is provided with a plurality of recesses on the first main surface. The conductive substrate is further provided with a plurality of holes in one or more portions each sandwiched between two adjacent ones of the recesses such that a region on a side of the first main surface has a larger porosity than a region on a side of the second main surface. The conductive layer covers the first main surface, side walls and bottom surfaces of the recesses, and walls of the holes. The dielectric layer is interposed between the conductive substrate and the conductive layer.


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