The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2024

Filed:

Nov. 01, 2021
Applicant:

Realtek Semiconductor Corp., HsinChu, TW;

Inventors:

Tse-Yi Hsieh, HsinChu, TW;

Ting-Ying Wu, HsinChu, TW;

Shu-Min Wu, HsinChu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 11/4072 (2006.01); G11C 11/4096 (2006.01); G11C 11/4093 (2006.01); G11C 29/10 (2006.01); G11C 29/02 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4072 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01); G11C 29/10 (2013.01); G11C 29/022 (2013.01);
Abstract

A method for performing memory calibration and an associated System on Chip (SoC) Integrated Circuit (IC) are provided. The method may include: in a power-up and initialization phase, controlling a physical layer (PHY) circuit within the SoC IC to apply power to a memory through a pad set and perform initialization on the memory; in an impedance-calibration-related phase, triggering the memory to perform impedance calibration regarding a set of data pins; in at least one subsequent phase, during performing any calibration operation among a reading-related calibration operation and a writing-related calibration operation, performing a data access test corresponding to a set of test points on a predetermined mask, wherein the predetermined mask is movable with respect to a data eye; and according to whether the data access test is successful, selectively stopping the any calibration operation.


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