The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2024

Filed:

Jan. 08, 2021
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Taoran Zhang, Beijing, CN;

Da Zhou, Beijing, CN;

Wenjun Liao, Beijing, CN;

Zailong Mo, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3233 (2016.01); G09G 3/3258 (2016.01); G09G 3/3208 (2016.01); G09G 3/325 (2016.01);
U.S. Cl.
CPC ...
G09G 3/3233 (2013.01); G09G 3/325 (2013.01); G09G 3/3208 (2013.01); G09G 3/3258 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0251 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01); G09G 2320/043 (2013.01); G09G 2320/045 (2013.01);
Abstract

A pixel circuit includes sub-pixel circuits each including a reset sub-circuit, a driving sub-circuit, and a light-emitting device. The reset sub-circuit is configured to input a voltage provided by an initial voltage terminal to the driving sub-circuit under control of a signal from a first reset control terminal. The driving sub-circuit is configured to control a driving current flowing through the light-emitting device according to a data signal output by a data terminal. The sub-pixel circuits include first and second sub-pixel circuits that are located in two adjacent columns, and connected to a same data terminal. A first reset control terminal and a writing control terminal of the first sub-pixel circuit are connected to first and second scanning signal terminals. A first reset control terminal and a writing control terminal of the second sub-pixel circuit are connected to second and third scanning signal terminals.


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