The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 2023
Filed:
Feb. 25, 2022
D-wave Systems Inc., Burnaby, CA;
Trevor M. Lanting, Vancouver, CA;
Danica W. Marsden, West Vancouver, CA;
Byong Hyop Oh, San Jose, CA (US);
Eric G. Ladizinsky, Manhattan Beach, CA (US);
Shuiyuan Huang, Eagan, MN (US);
J. Jason Yao, San Ramon, CA (US);
Douglas P. Stadtler, Morgan Hill, CA (US);
D-WAVE SYSTEMS INC., Burnaby, CA;
Abstract
Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures. The second material can be considered a low-noise material.