The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

Nov. 22, 2021
Applicant:

Key Foundry Co., Ltd., Cheongju-si, KR;

Inventor:

Su Jin Kim, Cheongju-si, KR;

Assignee:

KEY FOUNDRY CO., LTD., Cheongju-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 41/60 (2023.01); H10B 41/44 (2023.01); H10B 41/47 (2023.01); H10B 41/48 (2023.01);
U.S. Cl.
CPC ...
H10B 41/60 (2023.02); H10B 41/44 (2023.02); H10B 41/47 (2023.02); H10B 41/48 (2023.02);
Abstract

A semiconductor device includes a single poly non-volatile memory device including a sensing and selection gate structure, an erase gate structure, and a control gate structure. The sensing and selection gate structure includes a sensing gate and a selection gate, a bit line, a word line disposed on the selection gate, and a tunneling gate line. The erase gate structure includes an erase gate, and an erase gate line disposed near the erase gate. The control gate structure includes a control gate disposed on the substrate, and a control gate line disposed near the control gate. The sensing gate, the selection gate, the erase gate and the control gate are connected by one conductive layer. The erase gate structure implements a PMOS capacitor, an NMOS transistor, or a PMOS transistor. The semiconductor device includes a single poly non-volatile memory device including a separate program area and erase area.


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