The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

May. 26, 2022
Applicant:

Mediatek Inc., Hsinchu, TW;

Inventors:

Chih-Hsuan Lo, Hsinchu, TW;

Man-Shu Chiang, Hsinchu, TW;

Chun-Chia Chen, Hsinchu, TW;

Chih-Wei Hsu, Hsinchu, TW;

Tzu-Der Chuang, Hsinchu, TW;

Ching-Yeh Chen, Hsinchu, TW;

Yu-Wen Huang, Hsinchu, TW;

Assignee:

MEDIATEK INC., Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 19/625 (2014.01); H04N 19/124 (2014.01); H04N 19/122 (2014.01); H04N 19/18 (2014.01); H04N 19/176 (2014.01); H04N 19/423 (2014.01);
U.S. Cl.
CPC ...
H04N 19/625 (2014.11); H04N 19/122 (2014.11); H04N 19/124 (2014.11); H04N 19/176 (2014.11); H04N 19/18 (2014.11); H04N 19/423 (2014.11);
Abstract

Video encoding methods and apparatuses in a video encoding system receive an input residual signal of a current block by a shared transform circuit, apply horizontal transform and vertical transform by a shared transform circuit to generate transform coefficients, apply quantization and inverse quantization to generate recovered transform coefficients, apply inverse vertical transform and inverse horizontal transform to the recovered transform coefficients by the shared transform circuit to generate a reconstructed residual signal for the current block, and encode the current block based on quantized levels of the current block. The shared transform circuit and a coefficient buffer in the folded 4-time transform architecture reuse computation resources in each transform stage. In some embodiments of the folded 4-time transform architecture, a hierarchical design for block size grouping is implemented with fixed throughput for uniform hardware scheduling.


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