The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

Sep. 01, 2022
Applicant:

Psemi Corporation, San Diego, CA (US);

Inventors:

Walid Fouad Mohamed Aboueldahab, Wokingham, GB;

Aichen Low, Cambridge, MA (US);

Assignee:

pSemi Corporation, San Diego, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/07 (2006.01);
U.S. Cl.
CPC ...
H02M 3/073 (2013.01); H02M 3/077 (2021.05);
Abstract

Circuits/methods for controlling the startup of multiple parallel power converters that avoid inrush current or switch overstress in an added power converter or a power converter having fault conditions. Embodiments include node status detectors coupled to nodes within parallel-connected power converters to monitor voltage/current and configured in some embodiments to work in parallel with an output status detector measuring the startup output voltage of a power converter. With charge pump-based power converters, the node status detectors ensure that the power converter pump capacitors are charged while the output capacitor is charged as well. For such embodiments, a softstart period of startup may be considered finished if both the shared output capacitors and the power converter pump capacitors are charged to target values. Embodiments may also be used for fault detection during steady-state operation.


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